Non-volatile phase-change memories (PCMs) incorporate materials that have the ability to switch between phases having different electrical characteristics. For example, these materials can switch between a disorderly amorphous phase and an orderly crystalline or polycrystalline phase, and the two phases are associated with resistivities of considerably different values, and consequently with a different value of a stored data. For example, the elements of the sixth group of the periodic table, such as tellurium (Te), selenium (Se), or antimony (Sb), called chalcogenides or chalcogenic materials, may advantageously be used for phase change memory cells. In particular, an alloy made of germanium (Ge), antimony (Sb), and tellurium (Te), known as GST (having a chemical composition Ge2Sb2Te5), is currently widely used in these memory cells.
Phase changes may be obtained by locally increasing the temperature of the cells of chalcogenic material, through resistive electrodes set in contact with respective regions of chalcogenic material. Access devices, for example metal oxide field effect transistors (MOSFETs), are connected to the heaters and enable selective flow of an electric programming current through a respective heater. This electric current, by the Joule effect, generates the temperatures for a phase change. In particular, when the chalcogenic material is in the amorphous state, with high resistivity (the “RESET” state), a current/voltage pulse (or an appropriate number of current/voltage pulses) of a duration and amplitude is applied to enable the chalcogenic material to cool slowly. Subjected to this treatment, the chalcogenic material changes its state and switches from the high-resistivity state to a low-resistivity state (the “SET” state). When the chalcogenic material is in the SET state, a current/voltage pulse of an appropriate duration and a high amplitude is applied to cause the chalcogenic material to return into the high-resistivity amorphous state.
During reading, the state of the chalcogenic material is detected by applying a voltage that is sufficiently low so as not to cause a phase change, and by reading the value of the current that flows in the memory cell. Since the current is proportional to the conductivity of the chalcogenic material, the state of the material can be determined, and thus the data stored in the memory cell can also be determined. In general, PCMs allow advantages, which include a high scalability and reading speed combined with a low current consumption and a high efficiency.
A non-volatile PCM device generally includes a memory array having memory cells organized in rows (wordlines—WL) and columns (bitlines—BL). Each memory cell includes a storage element and an access element connected in series between a respective bitline BL and a reference potential terminal (for example, ground, GND). In particular, a wordline WL is defined by the set of all the control terminals of the access elements aligned along one and the same row.
The storage element includes a phase change material, for example, a chalcogenide, and is able to store data in the form of resistance levels associated with the various phases assumed by the material. The access element may include an N-channel complementary metal oxide semiconductor (CMOS) transistor having its gate terminal connected to a respective wordline WL, its drain terminal connected to the storage element, and its source terminal connected to the reference potential terminal. The access element is controlled and biased to enable, when selected, the flow of a reading/programming (modify) driving current through the storage element, having an appropriate value during respective reading/programming operations.
A column decoder and a row decoder enable selection based upon address signals received at the input of the memory cells, and in particular of the corresponding wordlines WL and bitlines BL, each time addressed, enabling biasing thereof to appropriate voltage and current values. The column decoder is moreover advantageously configured to define internally two distinct paths towards the bitlines BL of the memory array each time selected. For example, one path is a reading path to selectively create a conductive path between the bitline BL selected and a sense-amplifier stage to compare the current circulating in the addressed memory cell with a reference current to determine the data stored. The second path is a programming path to selectively create a conductive path between the bitline BL selected and a driving stage, which is configured to supply the high currents for generating the changes of state during the programming operations for the Set and Reset states.
In the specific case of PCMs, it is also known that the reading operations, as compared to the programming operations, use lower values for the biasing voltage applied to the wordlines to enable the desired current flow through the storage element, especially when selector transistors of a MOS type are used. For example, a value of 1.2 V may be used during reading and 2.8 V during programming. In this regard, memory devices of a work with two internally available supply voltages. This includes a first supply voltage Vdd having a logic value, generally between 1.08 V and 1.32 V, for example 1.2 V, and a second supply voltage Vcc, of a higher value, generally between 3 V and 3.6 V. Inside the memory device, intermediate voltages are moreover generated, for example by level-shifter stages, that are for the programming operations of the memory cells.
An example of an existing row decoder 20 is now described with reference to FIG. 1, where decoded signals are coupled to an input of an NAND gate 21. The output of the NAND gate 21 is applied to an input of a high voltage inverter 23 through an NMOS switch 22. The output of the inverter 23 is provided to the input of the inverter as feed-back through a PMOS switch 24 to force the input of the inverter 23 to a full positive voltage and to avoid static current consumption through the inverter. In addition, the output of the inverter is applied to an input of wordline WL driver circuitry, which further drives the wordline WLs in a memory array.
An example of an existing pre-decoder stage 30 is now described with reference to FIG. 2, which includes digital logic 31 and two level shifters 32, 33 that are used to translate low voltage to high voltage signals.
An existing row decoder 40 is explained with reference to FIG. 3. For example, pre-decoding stages include high voltage level shifters 32, 33 and high voltage logic 41, 42. The output of the pre-decoding stage is applied to the input of a high voltage NAND gate 43 and which further drives the high voltage wordline WL driver 44. In particular, the circuitry 40 includes high voltage transistors because high voltage is passed on to the wordline WL in the programming operation.
Due to the use of high voltage transistors in the row decoder (including pre-decoder and wordline WL driver), fast charging of the wordlines WLs may be impacted due to lower transconductance of the high voltage transistors. Accordingly, the read operation access timings may also be impacted. In addition, high voltage transistors are larger than low voltage transistors and use more area. Although the read operation is performed at low voltages, the high voltage level shifters are in the wordlines WLs charging path resulting in switching in the level shifters during the read operation. Accordingly, this results in more power consumption.